1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device and a method for rewriting data thereto. More particularly, the present invention relates to a non-volatile semiconductor memory device suitable for multi-value flash memories, such as flash EEPROM (Electrically Erasable and Programmable Read Only Memory) and the like, and a method for rewriting data thereto.
2. Description of the Related Art
Conventionally, an electrically rewritable non-volatile semiconductor memory device, such as EEPROM, flash EEPROM, and the like, comprises a memory array in which a plurality of memory cell transistors, each of which comprises a charge accumulation layer comprising a floating gate and an insulating film between a control gate and a semiconductor substrate, are provided.
By injecting electric charges into the charge accumulation layer or discharging electric charges from the charge accumulation layer, the threshold voltage Vth of the memory cell transistor is changed. By changing the threshold voltage Vth of the memory cell transistor in that manner, data is written into the memory cell transistor and the memory cell transistor stores the written data.
In order to write data into the memory cell transistor, for example, a voltage of 0 V is applied to a source diffusion region provided in the semiconductor substrate, a voltage of about 5 V is applied to a drain diffusion region, and a pulse voltage of about 12 V is applied to the control gate. In this case, the floating gate is not electrically fixed and is floating.
When a pulse voltage is applied to the control gate, the memory cell transistor is turned ON so that an electric current flows between the source and the drain. The electric current generates hot electrons. The hot electrons (i.e., electric charges) are injected into the floating gate and are accumulated therein. When the electrons are injected into the floating gate, the threshold voltage Vth of the memory cell transistor controlled by the control gate is increased. By associating the threshold voltage Vth with data xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d, two-value data can be stored in the memory cell transistor.
FIG. 9 is a graph showing the threshold voltage distribution of memory cell transistors in a two-value memory.
FIG. 9 shows the threshold voltage distribution of memory cell transistors when electrons are not injected into the floating gates thereof (corresponding to the left-hand distribution indicated by reference numeral 92) and the threshold voltage distribution of memory cell transistors when electrons are injected to the floating gates thereof (corresponding to the right-hand distribution indicated by reference numeral 94). Note that in the graph of FIG. 9, the horizontal axis represents the threshold voltage Vth of a memory cell transistor, while the vertical axis represents the number of memory cell transistors indicating a threshold voltage Vth (i.e., the number of bits).
One data value corresponds to one threshold voltage distribution. Threshold voltages corresponding to one data value are distributed in a certain range. As used herein, such a range is referred to as threshold voltage range.
The threshold voltage of a memory cell transistor is relatively low, as indicated by reference numeral 92, when electric charges are not injected into the floating gate thereof. The threshold voltage of a memory cell transistor is relatively high, as indicated by reference numeral 94, when electric charges are injected into the floating gate thereof.
Therefore, when a determination voltage which is located between the two threshold voltage ranges is applied to the control gate, a memory cell transistor whose floating gate does not receive injected electric charges (i.e., a memory cell transistor having the distribution indicated by reference numeral 92) is turned ON and a read electric current flows therethrough, and a memory cell transistor whose floating gate receives injected electric charges (i.e., a memory cell transistor having the distribution indicated by reference numeral 94) is turned OFF and a read electric current does not flow therethrough.
By detecting the presence or absence of the read electric current using a sense circuit, the sense circuit can read out data stored in a memory cell transistor as xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d, depending on the threshold voltage thereof. Thus, the ON/OFF state of a memory cell transistor is changed depending on a change in threshold voltage caused by electric charge injection into the charge accumulation layer (more specifically, floating gate) of the memory cell transistor, so that the threshold voltage of the memory cell transistor can be associated with data.
In recent years, a so-called multi-value memory technology has been proposed in which by regulating the amount of electric charges injected into a floating gate, more data values can be written into one memory cell transistor.
Such a multi-value flash memory is described in, for example, xe2x80x9cIEEE Journal of Solid-State Circuits Vol. 31, No. 11xe2x80x9d, November 1996, pp. 1575-1583. In the case of a four-value memory, for example, there are four threshold voltage distributions. Three determination voltages, each of which is located between two adjacent threshold voltage distributions among the four threshold voltage distributions, are applied to a word line connected to a control gate. Specifically, three read operations are carried out. In this case, an operation similar to the read operation of the two-value memory is carried out three times while changing the value of a determination voltage applied to a word line.
FIG. 10 is a graph showing the distribution of the threshold voltages Vth of memory cell transistors in a four-value memory. Note that in FIG. 10, the horizontal axis represents the threshold voltage Vth of a memory cell transistor, while the vertical axis represents the number of memory cell transistors indicating a threshold voltage Vth (i.e., the number of bits).
The threshold voltage of a memory cell transistor whose floating gate does not receive injected electric charges is relatively low as indicated by the left-hand most distribution in FIG. 10 (reference numeral 102). The threshold voltages of memory cell transistors whose floating gate receives injected electric charges are relatively increased with an increase in the amount of electric charges injected into the floating gate as indicated by right-hand distributions in FIG. 10 (reference numerals 104, 106, and 108).
It is now assumed that a certain determination voltage is applied to the control gate. If the threshold voltage of a memory cell transistor is lower than the determination voltage, the memory cell transistor is turned ON and a read electric current flows therethrough. If the threshold voltage of a memory cell transistor is higher than the determination voltage, the memory cell transistor is turned OFF and a read electric current does not flow therethrough. The three determination voltages are each applied, and the presence or absence of a read electric current is detected using a sense circuit. Thus, data stored in the memory cell transistor can be read, i.e., it can be determined which value the data has among the four values.
In general, the following phenomenon is known. Electrons are injected into the floating gate of a memory cell transistor so that the threshold voltage Vth of a memory cell transistor is increased to a prescribed value. Thereafter, the memory cell transistor is allowed to be idle. As the idle time is increased, the threshold voltage Vth of the memory cell transistor is shifted toward a lower value.
FIG. 11 is a graph showing that the threshold voltage Vth of a memory cell transistor is shifted as the idle time t of the memory cell transistor is increased. Note that in FIG. 11, the horizontal axis represents an idle time t, while the vertical axis represents a threshold voltage Vth.
As shown in FIG. 11, when the idle time of a memory cell transistor reaches t0, the threshold voltage Vth of the memory cell transistor is shifted to a level which is lower by a voltage xcex94Vth than the written threshold voltage Vth.
A cause of such a shift phenomenon is that electric charges (electrons) which have been injected to the floating gate of a memory cell transistor is discharged (leaked) from the floating gate over time. The leakage of electric charges from the floating gate can be suppressed to some extent by improving materials for the memory cell transistor. However, as the miniaturization of semiconductor memories is proceeding, the likelihood of electric charge leakage increases and the shift phenomenon is more likely to occur.
Hereinafter, a problem with the shift phenomenon of the threshold voltage Vth of a memory cell transistor will be described with reference to FIGS. 9 and 10.
As described above, as the amount of injected electric charges is increased, the threshold voltage Vth increases. As time goes, electrons are discharged from the floating gate of a memory cell transistor, so that the threshold voltage Vth of the memory cell transistor is shifted down, i.e., the threshold voltage Vth becomes lower.
In the case of a multi-value memory capable of storing three or more data values in one memory cell transistor, a margin between adjacent threshold voltage ranges is considerably small as shown in FIG. 10, and the shift of a threshold voltage Vth becomes not ignorable over time. A threshold voltage Vth corresponding to a certain data value may be shifted into a threshold voltage range corresponding to another data value. In such a case, if data stored in the memory cell transistor is read out, the data is departed from the original written data of the memory cell transistor due to the shift of the threshold voltage Vth.
In the case of two-value memories, as shown in FIG. 9, since the margin between adjacent threshold voltage ranges is relatively large, even a relatively large shift of a threshold voltage Vth is tolerable and has a small influence on data read.
However, when a power source voltage is reduced and the margin between adjacent threshold voltage ranges is not sufficient, a threshold voltage Vth is shifted toward a lower level over time as in multi-value memories, so that a threshold voltage Vth corresponding to a certain data value is shifted into a threshold voltage range corresponding to another data value. Also, in this case, if data stored in the memory cell transistor is read out, the data is departed from the original written data of the memory cell transistor due to the shift of the threshold voltage Vth.
In these circumstances, for example, Japanese Laid-Open Publication No. 9-35488 discloses a technique for preventing the alteration of data due to the shift of a threshold voltage over time. According to this conventional technique, a refresh function block is incorporated into a non-volatile semiconductor memory device. The refresh function block measures an elapsed time from the time of the last write operation for each memory chip or memory sector and compares the elapsed time with a prescribed limit of the electric charge holding time. If the elapsed time reaches the limit of the electric charge holding time, data is rewritten into each memory chip or memory sector.
Japanese Laid-Open Publication No. 9-306182 discloses a technique in which when a change in threshold voltage is detected in a specific memory cell transistor, data is written again into the memory cell transistor. Specifically, a detection means is used to determine whether or not a specific memory cell transistor has a threshold voltage at a detection point a prescribed distance away in a predetermined direction from the distribution of the threshold voltage immediately after a write operation. The data rewrite operation is carried out in the following manners: (1) data is erased and thereafter the original data is rewritten, or (2) a change in the threshold voltage of a memory cell transistor is compensated for without erasing data to recover the original data.
Japanese Laid-Open Publication No. 11-154394 discloses the following technique. An appropriate threshold voltage of a memory cell transistor is divided into a range corresponding to a permission state for data storage and a range corresponding to a forbidden zone indicating erroneous data. When a threshold voltage is shifted into the forbidden zone, a refresh operation is carried out to program the threshold voltage to the permission state. In the refresh operation, data in a memory cell is temporarily saved into a buffer, the data in the memory cell block is erased, and the data is rewritten from the buffer into the memory cell block. Such a rewrite operation is carried out by repeating a normal data write operation and a verify operation.
As used herein, the term xe2x80x9cverifyxe2x80x9d means to investigate whether or not data is written as is originally expected.
Japanese Laid-Open Publication Nos. 9-35488, 9-306182, and 11-154394 only describe that a change (shift) in threshold voltage is compensated for by repeating a normal data write operation and a verify operation. No specific method is illustrated.
Typically, a verify operation expends much time and effort. Therefore, the above-described repeating operation requires a relatively long time (about 10 xcexcs).
The above-described publications do not describe the level of a threshold voltage which is used to rewrite data.
According to an aspect of the present invention, a non-volatile semiconductor memory device is provided, comprising: a memory array comprising a plurality of memory cells, wherein each of the plurality of memory cells is capable of storing a plurality of data values depending on the voltages thereof, the plurality of data values include a first data value corresponding to a first voltage range and a second data value corresponding to a second voltage range, and the first data is written in one memory cell of the plurality of memory cells; a determination section for determining whether a voltage value of the one memory cell is higher or lower than a reference value set between a maximum value and a minimum value of the first voltage range; and a rewrite section for rewriting the first data into the one memory cell based on a determination result of the determination section so that a margin between the first voltage range and the second voltage range in the one memory cell is enlarged.
In one embodiment of this invention, the rewrite section shifts the voltage value of the one memory cell based on the determination result of the determination section so as to narrow the first voltage range.
In one embodiment of this invention, the rewrite section shifts the voltage value of the one memory cell by a prescribed value based on the determination result of the determination section.
In one embodiment of this invention, if the determination section determines that the voltage value of the one memory cell is lower than the reference value set between the maximum value and the minimum value of the first voltage range, the rewrite section increases the voltage value of the one memory cell by the prescribed value.
In one embodiment of this invention, if the determination section determines that the voltage value of the one memory cell is higher than the reference value set between the maximum value and the minimum value of the first voltage range, the rewrite section decreases the voltage value of the one memory cell by the prescribed value.
In one embodiment of this invention, the rewrite section shifts the voltage value of the one memory cell based on the determination result of the determination section so that the voltage value of the one memory cell is included in a range of the first voltage range on one side thereof relative to the reference value.
In one embodiment of this invention, each of the plurality of memory cells is a memory cell transistor comprising a charge accumulation layer for accumulating electric charges; and the memory cell transistor is capable of storing a plurality of data values depending on the amount of the electric charges accumulated in the charge accumulation layer.
In one embodiment of this invention, the rewrite section shifts the voltage value of the one memory cell by applying a write signal having a prescribed pulse width to the one memory cell.
In one embodiment of this invention, the reference value is set to a middle value of the first voltage range.
In one embodiment of this invention, the prescribed value is set to a difference value between the maximum value of the first voltage range and the reference value.
In one embodiment of this invention, the prescribed value is set to a difference value between the minimum value of the first voltage range and the reference value.
In one embodiment of this invention, the minimum value of the first voltage range is higher than a maximum value of the second voltage range; and the prescribed value is set to a difference value between the minimum value of the first voltage range and a determination value indicating a determination voltage for distinguishing the first voltage range from the second voltage range.
In one embodiment of this invention, the determination value is set to a middle value between the first voltage range and the second voltage range.
In one embodiment of this invention, the maximum value of the first voltage range is lower than a minimum value of the second voltage range; and the prescribed value is set to a difference value between the maximum value of the first voltage range and a determination value indicating a determination voltage for distinguishing the first voltage range from the second voltage range.
In one embodiment of this invention, the determination value is set to a middle value between the first voltage range and the second voltage range.
According to another aspect of the present invention, a rewriting method for a non-volatile semiconductor memory device is provided, comprising the steps of: reading a voltage of a memory cell capable of storing a plurality of data values depending on the voltage thereof, wherein the plurality of data values include a first data value corresponding to a first voltage range and a second data value corresponding to a second voltage range, and the first data is written in the memory cell; determining whether a value of the voltage of the memory cell is higher or lower than a reference value set between a maximum value and a minimum value of the first voltage range; and rewriting the first data into the memory cell based on a determination result of the determining step so that a margin between the first voltage range and the second voltage range in the memory cell is enlarged.
In one embodiment of this invention, the rewriting step comprises shifting the voltage value of the memory cell so that the voltage value of the memory cell is higher than the reference value if the determining step determines that the voltage value of the memory cell is smaller than the reference value set between the maximum value and the minimum value of the first voltage range.
In one embodiment of this invention, the rewriting step comprises shifting the voltage value of the memory cell so that the voltage value of the memory cell is smaller than the reference value if the determining step determines that the voltage value of the memory cell is higher than the reference value set between the maximum value and the minimum value of the first voltage range.
In one embodiment of this invention, the memory cell is a memory cell transistor comprising a charge accumulation layer for accumulating electric charges; and the rewriting step comprises reinjecting electric charges into the charge accumulation layer.
In one embodiment of this invention, the rewriting step comprises shifting the voltage value of the memory cell by applying a write signal having a prescribed pulse width to the memory cell.
Functions of the present invention will be described below.
According to the present invention, a memory cell is capable of storing a plurality of data values including a first data value corresponding to a first voltage range and a second data value corresponding to a second voltage range. It is determined whether the voltage value of the memory cell, in which the first data value has been written, is higher or lower than a reference value set between the maximum value and minimum value of the first voltage range. Based on a result of the determination, the first data is rewritten into the memory cell so that a margin between the first voltage range and the second voltage range is enlarged. Thus, by enlarging a margin between the first voltage range and the second voltage range based on the result of determination whether the voltage value of the memory cell is higher or smaller than the reference value, the data holding time of a memory cell can be elongated.
A transistor having a charge accumulation layer (a floating gate and an insulating film) is used as a memory cell, i.e., a memory cell transistor. By injecting electric charges into the charge accumulation layer to regulate the threshold voltage of the memory cell transistor, one data value or two or more data values is written into the memory cell transistor. In this case, threshold voltages corresponding to the same data value are distributed between the maximum value and the minimum value, due to variations in memory cell transistors or chips comprising the memory cell transistors, where the maximum frequency is located at the middle value or in the vicinity thereof. The threshold voltage distribution is shifted in a certain direction since electric charges are discharged from the charge accumulation layer over time. Thus, if the threshold voltage is shifted into a threshold voltage range corresponding to a data value different from that when a data write operation has been carried out, a data value different from the written data value is read out.
In general, leakage of electric charges due to idle causes the threshold voltage to be shifted to a lower value. An embodiment of the present invention provides a solution to avoid this as follows. The threshold voltage value is compared with a reference value set within a threshold voltage range. If the threshold voltage value is lower than the reference value, are write operation is not carried out. Only if the threshold voltage value is higher than the reference value, a rewrite operation (reinjection of electric charges) is carried out so that the threshold voltage value is increased by the prescribed value, i.e., the threshold voltage is shifted to a higher level. Thus, even if the threshold voltage is subsequently shifted down to some degree over time, the period of time during which the threshold voltage is maintained within the written threshold voltage range can be elongated.
Alternatively, the threshold voltage of a memory cell may be shifted to a higher level, since, for example, electric charges are leaked to the memory cell from other parts of the device. The present invention also provides a solution to avoid this. The threshold voltage value is compared with a reference value set within a threshold voltage range. If the threshold voltage value is lower than the reference value, are write operation is not carried out. Only if the threshold voltage value is higher than the reference value, a rewrite operation (redischarge of electric charges) is carried out so that the threshold voltage value is decreased by a prescribed value, i.e., the threshold voltage is shifted to a lower level. Thus, even if the threshold voltage is subsequently shifted up to some degree over time, the period of time during which the threshold voltage is maintained within the written threshold voltage range can be elongated.
For memory cells, a small (narrow) variation (distribution) in threshold voltage is preferable. A sufficient margin between adjacent threshold voltage ranges is preferable, particularly for a multi-value memory capable of storing 3 or more data values. Therefore, there is a demand for a considerably small threshold voltage range. In other words, if the threshold voltage range is narrow, a large number of data values (multi-value) can be stored in one memory cell transistor. By storing a number of data values in one memory cell transistor, it is possible to achieve a memory array having a small size and a large capacity.
Therefore, according to the present invention, the threshold voltage value is shifted by a prescribed value to one side (higher voltage side or lower voltage side) only if the threshold voltage value is lower or higher than a reference value. Therefore, it is possible to cause the threshold voltage value to be on one side (higher side or lower side) relative to the reference value. Therefore, the threshold voltage range can be further narrowed, so that a margin between adjacent threshold voltage ranges can be enlarged and the data holding property of the memory can be improved.
The reference value to be compared with the threshold voltage can be any value between the maximum value and minimum value of the threshold voltage range. If the threshold voltage distribution is laterally symmetrical and has a peak at the middle thereof, the reference value is preferably set to the middle value (or its close values) of the threshold voltage range. Thus, the threshold voltage value of a memory cell corresponding to a certain data value can be shifted to one side (higher or lower side) of the middle value of the threshold voltage range so that the threshold voltage range can be narrowed.
The prescribed value by which the threshold voltage is shifted can be any value. For example, the prescribed value maybe set to the difference value between the maximum value and middle value (e.g., a voltage value equal to xc2xd of the difference between the maximum value and minimum value of threshold voltage range) of the threshold voltage range. Alternatively, the prescribed value may be set to the difference value between the minimum value of a threshold voltage range corresponding to each data value (each value in a multi-value memory) and a determination value indicating a determination voltage for distinguishing the threshold voltage range from an adjacent threshold voltage range lower (or higher) than the threshold voltage range (e.g., a voltage value equal to xc2xd of the difference between the maximum value and minimum value of two adjacent threshold voltage ranges).
A write signal having a prescribed pulse width may be applied to the control voltage terminal (control gate) of a memory cell transistor requiring shift, once or a desired number of times, in order to shift the threshold voltage value by a prescribed value, a refresh operation can be quickly carried out.
Therefore, the operation time required for a rewrite (refresh) operation can be reduced as compared to conventional technique in which a write operation and a verify operation are repeated.
Thus, the invention described herein makes possible the advantage of providing a non-volatile semiconductor memory device in which a quick rewrite operation is carried out so that a margin between adjacent threshold voltage ranges is increased, thereby improving the data holing property; and a rewriting method.
These and other advantages of the present invention will become apparent to those skilled in the art upon reading and understanding the following detailed description with reference to the accompanying figures.